A field-effect transistor (FET) has three terminals: a gate, a drain and a source. The bias or operating point of the field-effect transistor is defined by the gate-to-source voltage (V.sub.GS), the drain current (I.sub.D), and the drain-to-source voltage (V.sub.DS). Presently there are two techniques for establishing the bias or operating point of an FET. The first technique is known as the two-supply biasing technique. The two-supply biasing technique requires two steps. In the first step a negative voltage supply is used to establish a gate-to-source voltage which, in turn, establishes a drain current. In the second step a positive voltage supply is used to establish a drain-to-source voltage. More specifically, the drain-to-source voltage is defined to be the voltage supplied by the positive voltage supply less a voltage drop created by the drain current passing through a drain resistor.
The primary advantage associated with the two-supply biasing technique is that the components used to implement it have a minimal effect upon the noise figure of the FET during AC operation. Noise figure is defined as the ratio of the actual noise power output of a device to an ideal noise power output for the device where the only source of noise is attributable to the signal being processed by the device. In other words, the noise figure is a quantitative measure of the noisiness of the device or the degree to which the device itself contributes to the amount of noise found in its output signal. The noise figure of a device is an important consideration in applications where the device is to process an input signal that contains significant, low-amplitude information since a device with a relatively high noise figure would bury or obscure the significant, low-amplitude information in its output signal.
However, certain characteristics of the two-supply biasing technique may render it unsuitable for certain applications. Namely, the two-supply biasing technique requires two voltage supplies of opposite polarity. Further, three resistors are required to implement the two-supply biasing technique: a two-resistor, voltage divider to establish the gate-to-source voltage and a drain resistor. Moreover, it is critical that the first step of the two-supply biasing technique be executed before the second step to prevent destruction of the FET. Consequently, sequencing circuitry is required to implement the two-supply biasing technique. Further, the two-supply biasing technique is temperature sensitive. Hence, in applications where the FET is exposed to broad variations in temperature and it is critical that the FET be maintained at a specific operating point implementation of the two-supply biasing technique requires the addition of temperature compensation circuitry. In addition, failure of either or both of the voltage supplies used to implement the two-supply biasing technique can result in destruction of the FET. Consequently, implementation of two-supply biasing technique in applications where failure of the voltage supplies is a possibility and the consequence thereof is unacceptable it is necessary to include circuitry that is capable of detecting the failure of either voltage supply and taking the appropriate action to prevent destruction of the FET.
With reference to FIG. 1, the second biasing technique is known as the self-biasing technique. In the self-biasing technique the operating or bias point of the FET is defined in a single step by a source resistor, a drain resistor and a positive voltage supply connected in series with the drain resistor. A bypass capacitor is connected in parallel with the source resistor to reduce the adverse effects of the source resistor on the gain and the noise figure of the FET during AC operation thereof.
The self-biasing technique exhibits several characteristics which, in certain situations, render the self-biasing technique superior to the two-supply biasing technique. For instance the self-biasing technique requires only one voltage supply. Furthermore, only two resistors are required to implement the self-biasing technique (i.e., the drain resistor and the source resistor). Moreover, no sequencing circuitry is required to implement the self-biasing technique since it is sequence independent. Further, temperature compensation circuitry is not necessary to implement the self-biasing technique since it is relatively insensitive to temperature variations. In addition, failure of the voltage supply used to implement the self-baising technique will not destroy the FET. Consequently, there is no need for circuitry to detect a voltage supply failure in implementing the self-biasing technique.
Despite such advantages, present structures utilized to define and/or implement a source resistor and a bypass capacitor for self-biasing and source bypassing are inadequate, from a noise contribution standpoint, where critical low-amplitude information carried by an input signal is to be processed and/or where use of a low-noise FET is otherwise required. Further, such known structures are particularly unsuitable due to noise contribution where high-frequency input signals (i.e., 1-12 GHz) are to be processed by current, high-frequency, low-noise FETs. For instance, such high-frequency, low-noise FETs are typically very expensive due to, among other things, the technology incorporated therein to overcome the increase in noise figure associated with the higher operating frequency. In such a situation, the noise contributed by current, self-biasing and source bypassing structures negates the low-noise figure advantage of such FETs and, hence, the investment in such FETs. Exemplary of known self-biasing and/or source bypassing structures are those shown in U.S. Pat. No. 4,183,041 to Goel, and U.S. Pat. No. 4,617,586 to Cuvilliers et al. As indicated, these structures and/or components fail to provide self-biasing arrangements and/or source bypassing that would suitably reduce noise contribution for the above-noted applications.
Presently, there exists a need for an FET biasing and bypass structure that is reliable, relatively insensitive to temperature variations, relatively light-weight and small, and that has a reduced effect on the noise figure of the FET. Moreover, there is a need for an FET biasing and bypass structure that can accommodate present packages embodying high-frequency FETs, i.e. FETs that operate in the microwave spectrum extending from 1-12 GHz, and especially high-frequency FETs with low noise figures. Such a need exists, for example, in high-frequency, space-based, surface imaging radar systems. In such systems, it is desirous to employ present high-frequency, low-noise FET packages that have laterally extending source leads.
In relation to such needs, the aforementioned two-supply biasing technique is capable of accommodating the low noise figure requirements. However, the self-biasing technique is clearly superior to the two-supply biasing technique with respect to the remaining criteria. More specifically, the need for two power supplies, sequencing circuitry, temperature compensation circuitry, circuitry for protecting the FET from voltage supply failures and the like renders the two-supply biasing technique unsuitable in comparison to the self-biasing technique. Moreover, the two-supply biasing technique is necessarily more complex and, hence, less reliable than the self-biasing technique. Given the drawbacks associated with the two-supply biasing technique, there exists a need for a self-biasing structure which exhibits a low noise impact and is otherwise acceptable with respect to the above-specified needs.
Further, there is a need for a self-biasing structure that can be readily assembled, preferably in a single step, and that is easy to inspect.